资源列表
ADC_AD7866_poll
- Module for AD7866 ADC po-Module for AD7866 ADC poll
ADS7835_2x4
- Module for 2 AD7835 ADC po-Module for 2 AD7835 ADC poll
Input_filter
- Module for filtering input digital signal
spi_3_wire_master
- Module SPI 3 wire master
FPGA-CPLD--learning-book
- 学习FPGA的入门资料，很全面的讲解，几个资料都很好-FPGA learning introductory information, very comprehensive explanation, several data are good
2_03_addder8
- 学习xilinx的简单模块程序，熟悉xilinx开发平台ise-xilinx demo code
7_06_FifoSim
- 学习使用xilinx的简单例程，熟悉ise平台-xilinx demo code
7_07_DCMSim
- 学习使用xilinx的简单例程，熟悉ise平台。DCM 仿真。-xilinx demo code
DIVIDER
- M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
nrf
- 基于fpga的无线传输nrfl24l01代码，这是发送和接收的代码，注意改下芯片的型号和引脚-nrf24l01 and fpga
shuzizhonganjian
- 设计一个数字钟，本设计要求一个12进制或24进制的具有时、分、秒计时功能的数字钟，并能进行时和分的调整。-Design a digital clock, this design requires a 12 or 24 hexadecimal hexadecimal have the hours, minutes, seconds, chronograph function digital clock, and can be adjusted hours and minutes.
ma_slice_temp
- verilog code temp h-verilog code temp hahahah