资源列表
spwm3
- 通过0，1序列来产生所需SPWM信号，带死区时间。可通过该SPWM信号通过H桥式电路控制电流形状。-The time required to generate SPWM signals with dead by 0,1 sequence. By H-bridge circuit to control the current through the SPWM signal shape.
jiaotongzhishideng
- 基于VHDL语言的交通指示灯设计。模拟交通指示灯来设计。-Based on VHDL design of traffic lights. Traffic lights to simulate the design.
CAN
- 包含CAN协议讲解与CAN协议控制器的verilog实现(含有testbench），该实现模仿SJA1000架构，接口完全一致。压缩包中还包含SJA1000的手册与应用指南，非常好的CAN学习资料。-CAN protocol controller implemented in Verilog（contain testbench） & instruction of CAN protocol & datasheet and user manual of SJA1000
distrbtdarth
- FIR FILTER DESIGNING USING DISTRIBUTED ARITHMETIC ALGORITHM
firfilterverilog
- FIR FILTER DESIGNED IN VERILOG FOR 4 BIT MULTIPLIER
carrysaveadder
- carry save adder for addition of 8 bit inputs
factoredcsd
- FIR FILTER USING FCSD TECHNIQUE FOR REPRESENTING COEFFICIENT
prefixadder
- prefix adder for addition of 2 inputs
counterbasedDPWM_D
- 基于计数器的数字脉宽信号调制，用于电力电子设备pwm信号的产生-counter based digital puls width modulator
delayline_b
- 基于延迟线的数字脉冲宽度调制，用于电力电子设备的触发信号产生-puls wide modulator based on delayline
s
- sram，np错误检测，对于sram中的np错误进行检测，具有非常好的速度以及故障覆盖率-sram, np error detection
Uart_TX
- 串口通信程序，可设置波特率，数据格式可更改-Serial communication program, you can set the baud rate and data format can be changed