资源列表
src
- 鼠标的verilog驱动，代码很短上电初始化后即可使用-Verilog mouse driver, code to initialize a very short period after the power to use
e001_vhdlsample
- vhdl 语言的例子,对初学的朋友很有帮助,值收藏!-VHDL language examples of helpful beginner' s Friend, the value of collections!
DDC_CIC
- 用CIC 和 FIR Filters设计的数字下变频器，DSP Builder6.1版工程文件-Using CIC and FIR Filters Design of Digital Down Converter, DSP Builder6.1 version of project file
newvhdl
- 在 Quartus II 7.1平台下，用VLDL写的一个计时器的程序-a timer written in VLDL in Quartus II 7.1 platform
Verilog_VGA
- 一个vga控制的FPGA代码，学习的好东西。-A vga control FPGA code, learning good things.
clock
- 用Verilog HDL 实现时钟(时和分)-designed Clock(minutes and second) by Verilog HDL
VHDL_da
- 大量的VHDL程序实例，供大家参考学习，是学习VHDL的好书。-VHDL procedures for a large number of examples for your reference
vhdl_cx
- 几十个VHDL源程序，可以学习借鉴，是初级程序员的好帮手。-Dozens of VHDL source code, you can learn from, is the primary programmer of a good helper.