资源列表
VHDLexamples
- VHDL案例代码，配套雷伏荣编的《VHDL电路设计》-Case VHDL code, matching Lei Fu-rong series "VHDL Circuit Design"
shuzizhongdianlu
- 利用计数器和分频器设计一个实时的时钟。一共需要1个模24计数器、2个模6计数器、2个模10计数器、一个生成1Hz的分频器和6个数码管解码器。最终用HEX5~HEX4显示小时（0~23），用HEX3~HEX2显示分钟（0~59），用HEX1~HEX0显示秒钟（0~59）。 -The use of counters and prescaler design a real-time clock. Mold needs a total of 24 counters, 2 Die 6 counters,
vga_card
- VGA模块的VHDL代码和软件驱动，可作为外设挂接在Avalon总线上。用一块SRAM作为显存，双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
VHDL100
- VHDL语言100例，通过例子了解VHDL语言。-VHDL language of 100 cases, through the example of VHDL language understanding.
RGBtoYCbCr
- 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件. -FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
modelsim_howto
- modelsim的使用方法,modelsim 是VHDL的仿真工具-how to use modelsim
ch2ex
- 部分电路模块的VHDL代码，包括组合逻辑与时序逻辑电路-Part of the circuit module VHDL code, including combinational logic and sequential logic circuit
ch3ex
- 部分组合逻辑数字电路的VHDL代码，包含必要的功能描述-Some combinational logic digital circuits VHDL code, containing the necessary functional descr iption
ch4ex
- 一部分简单时序逻辑电路的VHDL源代码，未包含状态机描述-Part of a simple sequential logic circuits VHDL source code, does not contain a descr iption of state machine
ch5ex
- 几个稍微深入的时序逻辑电路和状态机的VHDL代码-Several little-depth sequential logic circuit and state machine of the VHDL code
ch6ex
- 数字系统的简单设计，其代码为VHDL，采用行为级描述-A simple digital system design, its code for VHDL, the use of behavioral descr iption
ch7ex
- 简单数字系统的VHDL代码，综合了组合，时序，和状态机-Simple digital system VHDL code, a combination of combinations, timing, and the state machine