资源列表
datapath
- for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION-for FPGA IMPLEMENTATION, OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION
vhdlexample
- vhdl简单的例子程序，供初学者参考，有模板可以参考-VHDL example of a simple procedure, the reference for beginners, it can refer to the template
VHDL-Cookbook
- VHDL快速查看 入门手册 还有少量精品例子-VHDL Quick View Getting Started manual was also a small number of fine examples
bb
- CPLD可编程逻辑芯片上实现信号发生器的方法和步骤，系统采用自顶向下的设计方法，以硬件描述语言VHDL和原理图为设计输入，利用模块化单元构建系统。-CPLD programmable logic chip Signal Generator methods and steps system uses top-down design approach to hardware descr iption language VHDL and principles of map design input,
zhongbiao
- VHDL的数字电子钟程序，供初学者参考哦！-VHDL digital electronic clock procedures, for beginners reference Oh!
ADC_16bit
- VERILOG 16-bit Analogue-Digital Converter-VERILOG16-bit Analogue-Digital Converter
FIFO_2
- VERILOG Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
SYNTHPIC.ZIP
- The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the licen
PKUverilogPPT1-9PAGE
- 课件 北京大学verilogHDL PPT课件-Peking University verilogHDL PPT Courseware Courseware
Xilinx
- Xilinx可编程逻辑器件的高级应用与设计技巧 全面介绍Xilinx的CoolRunnerII Spartan-3 Virtex-II VirtexII pro等器件的结构特性，以及ISE6及其辅助设计工具。 -Xilinx programmable logic devices and design techniques for advanced applications a comprehensive introduction to Xilinx s CoolRunnerII Sparta
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
cam_test
- 一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog-CAM a verified source (CAM = Content Address Memory). Language for Verilog