资源列表
watchver
- 一个VHDL编写的时钟的程序，全部源代码打包上传-The clock to prepare a VHDL process, all source code packaged Upload
dds_using_FPGA
- 利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2，该环境集成了IP核，可以提高开发效率。-FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficiency.
vga_colors
- 该项目在VGA显示器上显示8色竖彩条。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on the monitor VGA color vertical color 8. VerilogHDL language used in Altera' s development environment QuartusII verification through.
Quartus7.2
- 通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计-4-bit full adder 8-bit full adder 8-bit register using vhdl
can.tar
- can控制器IP核，verilog语言描述实现。含测试例-can controller IP core, verilog language described realize. Containing the test cases
fpga
- FPGA 的教程 ,适合初学者，望有点启发-fpga
MaxPlusII
- MaxPlus II 简易用户使用入门指南，解释详尽，内容易懂-Simple user MaxPlus II Getting Started Guide to explain the detailed
ddszh
- 基于FPGA的DDS正弦信号发生器,信号失真小，频率稳定，可调-FPGA DDS shuzhi xinhao
cic_compiler_ds613
- cic_compiler_ds613 xilinx technology documents
VHDL_exmple
- VHDL编程一百例，包括加法器、乘法器、移位寄存器、奇偶校验器等。pdf格式的，仅供学习使用-VHDL Programming 100 cases, including the adder, multiplier, shift register, parity, etc.. pdf format, for learning to use
VerilogUSB
- 使用方法： 1.拷贝到硬盘，用ISE打开工程文件即可-Usage: 1. Copy to your hard disk, open the project file with ISE can
ps2_mouse
- ps2鼠标驱动,verilog 编写，代码很短，上电初始化后即可使用-ps2 mouse driver