资源列表
DSP_Builder
- DSP Bulider入门资料。适合初学者入手-the DATA of TI dsp bulider ,this manul can use for primier hander,and you can master dsp bulider fasterly
The-design-of-the-38-decoder
- 三八译码器的构成、原理与设计方法 VHDL语言的设计技巧-The design of the 38 decoder
The-state-machine
- 状态机实现序列检测器的设计，并对其进行仿真和硬件测试-The state machine implementation, the design of sequential detector and carries on the simulation and hardware test
pro11
- 异步fifo设计，使从B发送的数据能被A正确接收-Asynchronous fifo design, so that the data can be sent B to A is correctly received
openfire_core_latest.tar
- openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
conv-std-logic
- This the code for convert binary number to integer number using std logic vector function. -This is the code for convert binary number to integer number using std logic vector function.
aes
- Improved Method to Increase AES system Speed
FIFO-queue-using-a-DPRAM
- FIFO queiue using DPRAM goog project
RISC-CODE
- Design and Implementation of 16 Bit RISC Processor
EGPWS
- INTEGRATION OF EMERGENCY LOCATOR TRANSMITTER (ELT) OF AIRCRAFT WITH THE GLOBAL POSITIONING SYSTEM (GPS)RECEIVER - A VLSI DESIGN APPROACH
nand_controller
- this the nand flash controller having testbench and simulation model for nand flash in it-this is the nand flash controller having testbench and simulation model for nand flash in it
ahb_master_latest.tar
- IN THIS WE HAVE AHP bus master for burst data transfer