资源列表
waterled
- FPGA实现流水灯的程序，大家可以借鉴一下，当时学FPGA写的。-FPGA implementation of the program of light water, everyone can learn from the school FPGA was written.
uart_TEST
- verilog实现串口通信实例程序源代码，以在自己开发板上实现-Serial communication example verilog source code to implement in their own development board
DE2_115_Audio
- DE2-115开发板音频控制器测试源码，对fpga开发者提供参考-DE2-115 development board audio controller test source, provide a reference for fpga developer
class11
- uart串口发送模块，其中filter为按键消抖-Uart serial send module, where filter is the key to shake
24sCountdown
- 基于CPLD的24秒倒计时 计时的窗口显示分为数码管和发光二极管两部分，其中二极管部分表示数码管后一位，.0-.9或.00-.09，故本计时器精确度可以提高到0.01s-Based on CPLD 24 seconds countdown Timing window displays and LED digital tube is divided into two parts, where the diode portion represents a digital tube, .0-
Altera-Lab-2
- Altera Lab 2 for DE1 - Manual and Solution
DE0_VGA
- 基于fpga的VGA程序代码，已经测试成功-VGA-based fpga code has been tested successfully
verilog_lecture
- verilog课件，很好 很不错，讲的很仔细，适合新手学习用！-verilog courseware, very very good, said very carefully, for beginners to learn to use!
LCDcontrol
- verilog code for t6963 240128 lcd
SOPC_Builder
- SOPC架构建立实例，针对altera公司的DE2开发板，其他开发系统也可以用-based FPGA , SOPC construct experiment
S13_VIDEO_IN_S_VIDEO
- verilog语言，video程序。需要的-verilog+ vidio
my_cpu
- 计算机组成原理实验代码：单周期Cpu设计，附上检测指令， 在ISE 14.4通过检测-Computer Composition Theory Experiment Code: Cpu single-cycle design, attach detection command, by detecting the ISE 14.4