资源列表
shift_register
- 用VHDL编写的简单明了的位移寄存器，仅供参考。-Prepared using VHDL simple shift register for reference purposes only.
upsampler
- 一个用VHDL自行编写的完整可行的增采样系统，仅供参考-VHDL with a self-preparation of a complete and feasible by sampling system, for reference only
freq_meter
- freq_meter for amb sysmtem
lms_ad_filt123
- LMS Adaptive Filter-LMS Adaptive Filter
verilog
- 自适应神经网络算法，用于障碍物检测，基于FPGA可综合实验-Adaptive neural network algorithm for obstacle detection, based on the FPGA can be integrated experiment
CODE-HDL
- CODE HDL APPLICATION COUNT
prueba
- Test for VHDL just a student version
Versuch1.vhd
- Simply Hello World alias Hola with seven Segment unit
verilog_key_music
- 系统时钟50 MHZ 按键输入 蜂鸣器输出-The system clock is 50 MHz Press to enter Buzzer output
ethernet
- ETHERNET，程序我已经验证过了，没有问题，大家可以放心使用。-ETHERNET, I program has already been verified, no problem, you can be assured use.
led_seq
- 本程序我已经验证过了，没有问题，大家可以放心使用。-The Program I has already been verified, no problem, you can be assured use.
Matrix
- 本程序我已经验证过了，没有问题，大家可以放心使用。-The Program I has already been verified, no problem, you can be assured use.