资源列表
FIR_MAC
- filter design for chirp signal
DE2_D5M
- 在Quartus ii 10.0的环境下，实现了从D5M摄像头中读取Bayer数据并转化为RGB，通过SDRAM缓存，VGA控制器，输出到显示屏的Verilog代码-In Quartus ii 10.0 Read Bayer format from D5M camera and convert to RGB format, through SDRAM, output on VGA port.
riscpu
- 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
pci_verilog
- 一个pci接口的硬件描述语言的实现源代码,用verilog语言实现-a pci interface hardware descr iption language source code to achieve with verilog language
sdr_c_trl_verilog
- SDRAM 控制器的Verilog代码 经过综合验证过的.无截压密码-SDRAM controller Verilog code comprehensive test after all. No cut-off pressure Password
ml50x_schematics
- xilinx公司的virtex-5开发板原理图 需要的可以下载看一下 希望对你有帮助-xilinx company virtex-5 development board schematics can download look you want to help
ls12_mux16
- 一个16位乘法器的veriolog语言实现。使用初学着。-A 16-bit multiplier veriolog language. Use a novice.
blockram
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
VHDLExperiment01
- VHDL源码实例 相关源码-VHDL source code examples
nios22_demo
- nios实例源码 相关代码-the nios instance source related code
OpenRISC
- 一个开放的risc，已应用到实际中，可以借鉴的不少，大家-an open RISC, has been applied to practice, we can draw a lot, we look at
video_from_opencore
- 全电视信号编码器，verilog的，看看有借鉴价值否？-video signal encoder, Verilog, to see whether the reference value?