资源列表
crc_32_8_fsm
- 循环校验码编码，并行编码，通过了FPGA测试验证-crc_encode, parallel coding, verified by FPGA
VHDL
- 通过一种新的方法来进行同步时钟提取，来自于美国某大学实验室-vhdl
cic-1
- cic滤波器2倍抽取verilog代码及testch-cic filter decimation verilog code and testch
BoothMultiplier
- -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthe
pre_norm_sqrt
- 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
electroniccodelockvhdl
- vhdl的电子密码锁This is based on the electronic code lock vhdl curriculum design code- the electronic code lock vhdl curriculum design code
lcd
- 这是学习FPGA的学习代码，语言是VHDL，主要控制LCD12864的显示。-This is learning FPGA learning code, the language is VHDL, the main control display LCD12864.
PWM
- 基于Avalon总线的PWM的实现，verlog语言编程-PWM-based Avalon bus implementations, verlog language programming
timer
- 基于vhdl的单片机最小系统定时器模块。Timer模块-Timer Module
verilog-hdl
- 本设计是以四路抢答为基本概念。从实际应用出发,利用电子设计自动化( EDA)技术,用可编程逻辑器件设计具有扩充功能的抢答器。它以Verilog HDL硬件描述语言作为平台，结合动手实验而完成的-The design is based on four basic concepts answer. From the practical application, the use of electronic design automation (EDA) technology, using a prog
sync_module
- fpga 关于verliog vga 7123的程序代码
AsynCFIFO
- 跨时钟域，异步的FIFO，利用指针移动，数据不移动，通过两级锁存消除跨时钟域的信号竞争-Cross clock domains and asynchronous FIFO, use the pointer to move, do not move the data, eliminating cross clock domain signal through a two-stage competition latch