资源列表
fifo8
- FIFO 源程序，verilog HDL实现，自己验证过，没问题-FIFO source, verilog HDL to achieve their own verified, no problem
display-seg
- 七段数码管驱动电路，fpga，seg7，altera开发板例子-risc-cpu design，seg7，fpga
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
i2s_to_parallel
- wm8731音频采集芯片的I2S采集时序的vhdl实现。-wm8731 I2S audio capture chip timing acquisition vhdl implementation.
八位的伪随机数产生的verilog文件
- 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
ALU
- VHDL实现ALU的源代码，并且提供了一个详细的testbench-ALU VHDL source code implementation, and provides a detailed testbench
conv_12_adpcm
- adpcm编码verilog程序,包含pcm转换模块、adpcm编码输出模块-ADPCM coding verilog procedures, including PCM conversion module, ADPCM encoding output module
Code
- 带丢包的线性均方最小方方差滤波器，这是在经典的kalman滤波器基础上修改的-LMMSE for systems with packet dropouts
shift_arr
- This contains the shift array which can be used in 2D DCT with help of 2 1D DCTs.
Piplined_RCA
- Pipelined Ripple Carry Adder verilog source file
eight_bit_spi
- Interface for SPI bus words 8bits with availability to loop the exchange