资源列表
RAW2RGB.v
- RGB-raw2RGB converting data from Cmos camera to FPGA
dianziqin
- 电子琴， 利用实验箱的脉冲源产生1，2，3，。。。共7个或14个音阶信号； 用指示灯显示节拍；能产生颤音效果。-Organ, using a pulse source generated test cases 1,2,3,. . . A total of 7 or 14 chromatic signal with the indicator shows the beat to produce vibrato effects.
adc_master_0730
- 关于ADS7864的驱动电路verilog代码设计，支持Avalon总线-The driver circuit on the ADS7864 verilog code design, support Avalon bus
Chronometer
- Chronometer VHDL code.
jtd
- VHDL实现交通灯-VHDL traffic lights
chufaqi
- 时序电路是指它的输出不仅取决于当时的输入，而且也取决于过去的输入，即过去输入不同，则在当前的情况下，输出也可能不同。-Sequential circuit is the output depends not only on its input at that time, but also on past input, that is different from the last input, then in the current circumstances, the output also
elevator
- This is a project about a elevator(lift). It can go up/down , stop . Will show the number of the floor on which it is at that moment,
clock
- 有防抖模块的双键数字钟，可实现时分秒调节，24小时计时。-There are double anti-shake digital clock module, minutes and seconds can be achieved when the regulation, 24-hour clock.
cordic
- we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentia
qiangdaqi
- verilog hdl实现的三路抢答器，一个复位键，八个数码管，五个LED灯，晶振为12 MHz 采用CPLD 器件为ALTERA 的EPM7064SL-44芯片 -verilog hdl implementation of three-way Responder, a reset button, eight digital control, five LED lights, crystal is 12 MHz ALTERA CPLD device is using the E
Part-2
- part structure for lab 2
cnt2
- 16位二进制计数器及设计代码其测试代码（vhdl）-16-bit binary counter and design codes and test code (vhdl)