资源列表
s_pandp_s
- 用VHDL编写的并串转换和串并转换实例，希望对您有所帮助，其中输入数据是时钟的16倍-prepared using VHDL and string conversion and string conversion and examples, and I hope to help you, the input data which is 16 times the clock
taxitwo
- 出租车计价器收费系统能更加准确，实现各种功能。-Taxi meter charging system can be more accurate, to achieve various functions.
tra_control
- 基于Maxplus2的Verilog编程，实现交通灯功能（包含倒计时）
inverter
- rc5的decryption，同样带state machine，同样有四个状态-RC5 of decryption, with the same state machine, the same four state
booth
- booth乘法器电路，基四实现，附带有testbench
PSO1
- i have coding for verilogHDL and VHDL. so please i want know that coding-i have coding for verilogHDL and VHDL. so please i want know that coding..
led
- led流水灯程序，已经验证过，很有用的哦！-led water chase, has already been verified, Oh, very useful!
ARM_37numbers_32bits
- ARM架构下的32位37个寄存器组的verilog源码-ARM architecture 32 37 register banks verilog source
LCD1602
- 液晶1602的FPGA驱动程序，可实现16x2的字符显示-1602 FPGA LCD drivers, enabling 16x2 character display
FIFO
- 用verilog语言编写的FIFO文件，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令，希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, h
cymometer
- 硬件频率计的实现，包括十分频，门控信号产生，频率测量等-cymometer implementation， involving 10 times divider, generating gate controling signal and frequency measurement
DE2_Basic_Computer
- DE2 altera board vhdl design