资源列表
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
vhdl-wenjian
- 这是我的VHDL格式的电子密码锁源程序，请站长审核啊-This is my VHDL source code format of the electronic lock, please review ah owners
lcd1602
- FPGA，通过VHDL语言编程，来控制并点亮LCD1602-FPGA control LCD1602
16bit_ram
- 利用vhdl语言在fpga实现十六位的ram 使用非常方便-Using vhdl fpga implementation sixteen languages in the ram is very convenient to use
clock_divider_lab
- Clock divider lab uusing xilinx tools, and simulator like modelsim
chufaqi
- 介绍了一种使用可编程逻辑器件FPGA和VHDL语言实现32位除法器的设计方法。该除法器不仅可以实现有符号数运算,也可以实现无符号数的运算。-A programmable logic device FPGA and VHDL design of the 32 divider. The divider can be achieved not only symbolic arithmetic, unsigned op.
circle
- VHDL routine to draw a circle using the midtpoint algorithm.
Booth-co-so-2
- Radix Booh 2.nice to see u.i uploaded this file to download the file that i need actually
pinglvji
- 频率计设计，实验过，好使，希望能帮到大家-Frequency meter design, experimental, so that, I hope to help everyone
counter
- 关于FPGA实现的几种计数器的verilog源程序-FPGA implementation of several counter verilog source code
voxel_image
- image descr iption ri really good
verilog_AD7886
- verilog实现模数转换器AD7886的仿真-verilog describe AD7886