资源列表
chuankou
- 串口VHDL实现 -Serial Serial VHDL realization of VHDL
clock_counter
- 一个简易的时分秒自加计数器，没有设置功能-hour-minute-second counter
TERASIC_ISP1362
- sopc中ISP1362的IP核，经验证，可以使用，保证正确！-sopc the ISP1362 the IP core, proven, you can use to ensure correct!
time-divider
- 时钟分频器，这个虽然简单一点，但还是觉得很不错的，-Clock divider, this is simple point, but still felt very good,
alarm
- vhdl alarm design code-vhdl alarm design code
lcd12864
- 基于FPGA的Verilog语言的LCD12864显示程序，测试通过-LCD12864 FPGA Verilog language-based display program, tested
122222222FFT
- 基于FPGA的FFT编码器和译码器的实现源代码-the decoder and encoder based on FPGA
xianshi
- lcd1602驱动程序 verilog语言-lcd1602
Desktop
- 四D触发器，最优先级编码器和加法器描述的VHDl文件-Four D flip-flop, the priority encoder and adder descr iption of the VHDl files
uarts
- RS-232 interface example for FPGA/EDA developers
ports
- 端口 嵌入式单片机端口设置 连接 VHDL实现-Port embedded microcontroller port settings to connect
shuzhuanglvboqi
- verolog语言编写，功能如标题所示。有问题请联系mxkmxm@126.com-verolog language, functions such as the title indicates. There are problems, please contact mxkmxm@126.com