资源列表
2
- 详细功能、包含内容说明 :时钟2倍频vhdl描述,-It very important data
pinlvjin
- 基于FPGA的频率计模块设计，带quartus下的图形文件-FPGA-based modular design of the frequency meter with graphics files under Quartus
encoder-8b10b
- 可以实现8b10b编码，verilog源程序，经过测试-8b10b Encoder
vga_dis
- 该代码设计在VGA显示器上显示背景蓝色，中央绿色边框和粉色矩形。-The code is designed to display on a VGA monitor background blue, central green border and pink rectangle.
muxsend
- 调用已绑定的网口 发送vlan包。适用于再次开发中遇到网口已被底层绑定的需求。-Call the net mouth has been bound to send vlan packets. For re-development of the net mouth has been encountered in the bottom bound needs.
-led_seg7
- 数码管显示代码。希望数码管显示什么数字，只需要给数码管段选口送去相应译码信号。-Digital display code. What hope digital display digital, just give digital tube segment selector sent to the corresponding port decoded signal.
jk-filpflop
- 这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的-This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met
user_encoded_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
lms_ad_filt123
- LMS Adaptive Filter-LMS Adaptive Filter
VGA_Module
- 用VGA LCD显示汉字，已经调试过，没有错误，尽可下载-it can be used to display word on VGA
display
- display_stim.vhdl Testbench for display Benchmark
verilog--password-lock
- 基于ＦＰＧＡ的密码锁 verilog- verilog FPGA password lock