资源列表
timer3
- 基于FPGA的VHDL时钟程序 本程序是基于FPGA的时钟程序,可用按键控制较时,有秒闪,调时指示!!!
digital_seven_segment_clock
- digital seven segment clock
doublefloat_RAM
- 使用verilog编写的一个双浮点RAM，支持对字、字节、半字、双字的读写，包含testbench和wave.do文件-Use verilog to implement a double float RAM, supporting the read and write of halfword,byte,word,double word. It includes the testbench and wave.do
hello_world_multi
- altera NiosII multicores hello_world_multi.c-altera nios ii
16-parallel-multiplier
- 简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
61EDA_H173
- Verilog设计的求复角的源代码(通过仿真验证的)-Verilog design of seeking re-angle the source code (through the simulation of the)
cordic_parameteizaed
- Verilog实现三角函数（基于CORDIC算法）-Verilog realization of trigonometric functions
freqconv
- In digital signal processing, a digital down-converter (DDC) converts a digitized real signal centered at an intermediate frequency (IF) to a basebanded complex signal centered at zero frequency. In addition to downconversion, DDC’s typically decimat
VGA_Controllerin-vhdl
- VHDL VGA controller that can controller the video (vga) scgy sginals
dds
- VHDL编的CPLD正弦波产生程序用直接数值合成DDS原理驱动dac0832实现正弦波输-VHDL compiled CPLD sine wave generation process by direct numerical synthesis of theory-driven dac0832 achieved DDS sine wave input
111
- Xilinx单片机 通过低通滤波实现示波器XY双通道输出点并且控制运动轨迹程序
i2c_slave_model
- IIC总线实现源码，调试通过可用，通信用-IIC bus to achieve source code, debugging through the available