资源列表
dattransf.rar
- 基于VHDL的10位定点数转浮点数模块源代码，可综合,VHDL-based set of 10 points to float the source code modules can be integrated
用VHDL实现布斯算法
- 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me.
DC
- 汉明码的解码电路，用VHDL实现，可以用于FPGA仿真-Hamming code decoding circuit, VHDL implementation, can be used for FPGA simulation
Project
- Design a sequential circuit that has two inputs w1 and w2 and an output z. A clock and a reset signal are also present. Its function is to compare the input sequences on the two inputs. If w1 ≠ w2 during any two consecutive clock cycles, the ci
VerilogDHL_clock
- 新来匝道穿上别人写的基于vhd的数字时钟很好大家看看啊，很规范的哦。-New ramp to wear someone else wrote vhd on the digital clock very well take a look at the ah, oh, very norms.
Keyboard
- Keyboard part of the source code in vhdl
jianpan
- 基于FPGA的Verilog的控制PS2数字小键盘并在数码管显示相应的数字-Verilog FPGA based control of PS2 numeric keypad and digital display the corresponding number
Seq_det_binary
- FSM Seq detector in binary encoding
RS232
- RS232_串口通信的发送端verilog源程序代码-RS232_ serial communication sender verilog source code
ADC-ADS7230
- ADC ADS7230 - ADC module in VHDL for ADS 7230 (Texas Instruments)
84_REG
- vhdl 语言 开发 程序比较详尽 微处理器 里面的部件-vhdl language development program inside the more detailed parts of the microprocessor
Chapter15-Adder
- 书籍《精通Verilog HDL语言编程》中第15章的程序实例代码，是关于常用加法器的设计的，对于初学者有一定的帮助-Books "Proficient in Verilog HDL language programming" in Chapter 15 of the procedure code, common adder design have some help for beginners