资源列表
multi_fre_timesim
- 采样时钟程序:在波特率为9600的采样时钟程序-multifrequency program. The baud rate for the 9600 multifrequency program
vga_display
- 采用VHDL语言针对spartan3e开发板写的VGA例程，包含.ucf配置文件-VHDL language used to write for spartan3e development board VGA routines, including. ucf profile.
led-cortol
- verilog hdl led 时序控制-led cortor with verilog hdl
vga_contr
- Vga controller. Implementation of VGA controller
GCD-CALCULATOR
- GCD CALCULATOR (ESD book figure 2.11) Weijun Zhang, 04/2001 we can put all the components in one document(gcd2.vhd) or put them in separate files this is the example of RT level modeling (FSM + DataPath) the code is synthesize
inter_deleaver
- This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.
timer_0
- 计数器的FPGA控制程序，开发平台为ISE或者quartus-FPGA counter control procedures, development platform for the ISE or Quartus
New-folder
- VHDL codes for booth , nco and some more
Integrator-comb_timing-state
- 积分梳状滤波器和时序状态机的Verilog语言描述，适合硬件描述初学者-Integrator-comb filter and timing the Verilog language to describe state machines, hardware descr iption suitable for beginners
FLASH_read
- 对spi接口的flash操作，用VHDL语言实现，read控制，串行输入，可以1位、2位、4位读出-Spi interface on the flash operation, with the VHDL language, read control, serial input, to one, two, four read
DianTiKongZhiQi-VHDL
- 电梯控制器VHDL程序，包含记忆，上升，下降，停站等功能，以及超载，故障后报警功能.rar-Elevator controller VHDL program, including memory, up, down, stop and other functions, and overloading, failure alarm. Rar
clock--the-end
- 多功能数字钟 24小时计时 整点报时功能 闹钟设置功能 校时 复位等-Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc