资源列表
tp-vhdl
- compteur digital VHDL 1ERE VERSION
ALU
- Arithmetic logic unit
ALU4
- arithmetic logic unit
sin.tar
- 神奇的sin波生成verilog源码，非常简单的代码无需乘法即可生成sin,cos，值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
spi
- spi 驱动Verilog代码 可以配置任意模式长度，时钟最高支持50M（再高没有测试过）-spi driver
VHDL_Bough_64-bit-twos-complement-multiplier
- VHDL Ccode_Booth two s complement multiplication
RS_232_Test
- this file is a driver for rs-232 protocol. tx and rx. working for as uart protocol
spi_4_2ch
- FPGA spi接口源码，可实现两个从机，扩展后可快速实现多从机，设置灵活，简单方便，有注释-FPGA spi interface source code, can achieve the two slaves, after expansion can quickly achieve multiple slaves, set flexible, easy to use, there is a comment
encoder
- VHDL实现循环码编码，设计了三个单元。switch是一个开关，shifter是移位寄存器，encoder是主体。
7_decoder
- VHDL编写！数据选择器大全！ 包括： mux2to1.vhd 二选一电路 mux2_1.vhd 二选一电路 mux2_1.bdf 二选一电路 mux3to1.vhd 三选一电路 mux3to1_1.vhd 三选一电路 mux4to1.vhd 四选一电路 -VHDL write! Data selector Daquan! Including: mux2to1.vhd two choose a circuit mux2_1.vhd two choose a cir
digi_cpld_lcd
- Digital clock implementation using VHDL-Digital clock implementation using VHDL
USBDataAcquire_Instance
- 在CY68013的FIFO模式下实现FPGA从USB中获取数据-In CY68013 the FIFO mode the FPGA to get data from the USB