资源列表
75_RAM
- ram的硬件描述 使用VHDL语言 注释也十分详细 想要的赶紧下载吧-ram using VHDL hardware descr iption language is also very detailed notes quickly want to download it
add_3p
- 3级流水线，含4元件的22位全加器的VHDL语言实现，适用于altera系列的FPGA
clk_div
- Clock devider in VHDL code
paixu
- 给定一个带期限的作业排序问题, n=5, (p1,p2,p3,p4,p5)=(6,3,4,8,5), (t1,t2,t3,t4,t5)=(2,1,2,1,1), (d1,d2,d3,d4,d5)= (3,1,4,2,4), 应用FIFOBB求使总罚款数最小的可行作业集J, 要求:实现对不同作业排序问题实例的求解，问题实例的输入数据存储在case.txt文件中。-Given a scheduling problem with the operation period, n = 5, (p1, p
fifo
- 异步FIFO源代码，由模块调用自动生成，不包含测试向量。-Asynchronous FIFO source code automatically generated by the module calls, does not contain the testbench.
control_fenpin
- 用spartan3对芯片AD9512通过SPI协议进行分频设置-spartan3 controls chip AD9512 divider Settings through the SPI protocol
biss_master_ad36_1217
- biss-c编码器读代码，测试好用，时钟要求40m -VHDL code about biss-c slave part.
ahbmst
- amba总线的主设备用于实现基于amba总线的功能，这个事主设备的代码-amba bus for the main equipment amba bus based on the function of the code of the victim equipment
75_RAM
- vhdl语言写的ARM程序，语法举例使用，实用模块， -ARM program written in vhdl language, grammar, for example the use of practical modules, vhdl language to write the ARM program, the syntax for example the use of practical modules,
fet410_ta_uart9600
- 430单片机定时通讯，异步通讯，9600波特率，32k晶振-430 timer chip communication
IS61WV51232BLL
- 这是SRAM-IS61WV51232BLL在NIOS软核应用下的读写时许代码。-This is SRAM-IS61WV51232BLL under NIOS soft-core application code reader o' clock.
autosell
- 自动售货机的FPGA设计代码 -FPGA design code of vending machines vending machines FPGA design code