资源列表
LDPC_Behavioral_VHDL
- 用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
shizhong
- 这个VHDL与其他上传的代码不同，这个代码更适合于初学者。电子时钟已经在硬件上得到成功仿真。-From the VHDL code with other different, the code is more suitable for beginners. Electronic clock has been successful in the hardware simulation.
HELLO
- 实现HELLO的移动，频率为1秒，仿真通过能使用在de2开发板上-Achieve HELLO mobile frequency of 1 second simulation through de2 development board
digtal
- 时、分、秒、实现数字钟的基本VHDL源代码。-Digital clock basic VHDL source code.
ram2
- RAm的 verilog描述，在Quartus中验证正确，可根据程序改成其他参数-Verilog descr iption of RAm in Quartus verify correct procedures can be changed in accordance with other parameters
code
- SHA_1算法填充部分的VHDL实现，让输入的数据可以转换为SHA_1算法所需要的512bit的数据-SHA_1 algorithm filling part of the VHDL realization, let the input data can be converted to SHA_1 algorithm need 512 bit data
VHDL
- 基于vhdl数字密码锁额外负担二十分我饿贫困方-vhdlewfkwefjwqewfkgqerjgqegqfrgfqer
12
- 单片机用1602 lcd与ds18b20设计的温度报警器程序，虽不可仿真，但可参考-Canopy temperature control system design and implementation
hdb3
- hdb3编解码程序，非常简洁好用，欢迎下载-hdb3 codec program is very simple to use, welcome to download
rs422_t
- 此功能模块实现了422标准协议的单字节发送功能，采用了起始位＋8位数据位+奇校验+1停止位的方式，实现了并行输入串行输出的功能。-This function module implements the standard protocols 422 single-byte transmit function, the start bit+ 8 data bits odd parity+1+ stop bits, enabling a parallel input serial output.
adcdac_modify
- ADC-DAC VHDL Working code for Spartan 3/3E FPGA device
FIFO
- Nios ii fifo,用于MCU通过nios ii进行fifo通信,verilog格式.-Nios ii fifo, for MCU FIFO communication, through the Nios II Verilog format.