资源列表
直方图统计的Verilog实现
- chengxu:直方图统计的Verilog实现，大家可以共同学习
top
- FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变-FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping
gen_tb
- 用于verlilog自动产生testbench的脚本 用法：gen_tb <yourfilename>-Testbench for verlilog automatically generated scr ipt usage: gen_tb <yourfilename>
sourcecode
- bit adder full adder upcounter encoder multiplier
ac97.v
- AC97音频传输协议的。Verilog语言程序-AC97 Verilog program
sram+lcd
- 用vhdl格式写的sram源代码，把扩展名txt改为.v即可
I2c_EEPROM
- I2C VHDL simulation, creates i2c with vhdl for simulation purposes. use it at your own risk.
my_counter
- this files are vhdl code
FeedBack_FSK_M30
- 基于EDA技术的专用调制解调的VHDL语言设计-EDA technology based on specific design of modulation and demodulation of the VHDL language
NEW_LCD_DRIVER
- VHDL code for HD44780 16x2 character LCD
PCI_IF_AMCC-S5920.ZIP
- Design for PCI IF AMCC S5920
DS18B20
- 由于18B20时序要求严格，一般不建议采用niosii来实现对他的驱动。本人自己编写的基于NIOSII驱动函数，50MHz主频，保证可用，温度精确到0.0625度。-Due to stringent timing requirements 18B20 generally not recommended niosii to achieve his driver. I have written based on NIOSII driver function, 50MHz frequency, can