资源列表
liushuideng
- 流水灯，控制方向，对系统时钟进行分频，奇偶数闪亮-Water lights, control direction, the system clock frequency, odd even flashing
pinlvji-design-VHDL
- 使用Altera公司的EP2C35系列的FPGA芯片，利用SOPC-NIOSII-EP2C35开发板设计和仿真一个数字频率计，对1Hz~250KHz 的脉冲进行频率测量，采用等精度测量，即在所测量的整个频段内部，均可实现相同精度的测量，测量精度与频率无关，结果在数码管上显示-The use of Altera EP2C35 series FPGA chip using the SOPC-NIOSII-EP2C35 board design and simulation of a digital
breath_led
- verilog breath led sourece code
buzzer_sos
- 蜂鸣器源代码buzzer code verilog-buzzer code verilog
display_sm
- 数码管扫描verilog源代码 display code verilog-display code
uart
- 串口verilog源代码 uart code verilog-uart code verilog
uart_back
- 串口回传verilog源代码 uart back code verilog-uart back code verilog
7seg
- 7seg.rar this file is use to fpga(altera) HEX-7seg verilog/VHDL-
slavefifo
- FPGA 3D camera experiment
mt46v16m16p_ddr
- 官网下载的，经过板级验证的ddr control mt45v16m16p源代码，verilog语言设计，希望可以用到系统化设计。-Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design.
vhdl_CRC_generatir
- CRC 產生器，VHDL 語言， 適合 FPGA 練習使用-CRC generator , VHDL language, Good for FPGA learnning
reg
- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out