资源列表
and_gate
- this program is done in verilog hdl and it is program of AND gate gate level modeling program-this program is done in verilog hdl and it is program of AND gate gate level modeling program
and_data
- this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program
and_beh
- this program is done in verilog hdl and it is program of AND gate BEHVIORAL level modeling program-this program is done in verilog hdl and it is program of AND gate BEHVIORAL level modeling program
nand_gate
- this program is done in verilog hdl and it is program of NAND gate gate level modeling program-this program is done in verilog hdl and it is program of NAND gate gate level modeling program
nand_data
- this program is done in verilog hdl and it is program of AND gate DATA level modeling program-this program is done in verilog hdl and it is program of AND gate DATA level modeling program
adc0809
- adc0809的时序控制，已经过modelsim验证，请大家多多指教，一起学习-adc0809 timing controll
sp6_BoardTest
- 针对xilinx spartan6芯片做的测试板测试用例-xilinx FPGA product SPARTAN6 test example
CD1_PHOTO_ABLUM_1280
- 基于FPGA的数码像册实验，使用了NIOS做文件系统和JPEG图像解码FPGA和SDRAM做了图像缓存-Based on the FPGA digital image book experiment, using the NIOS to do file system and JPEG image decoding FPGA and SDRAM do the image cache
CD1_PHOTO_ABLUM_1920
- 使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存-Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache
CD1_MT9V034_RAW_TRANS
- 基于FPGA的UDP网络图像传输实验，FPGA完成了MT9V034的RAW图像采集缓存，NIOS完成了图像的UDP封包，DM9000芯片完成了MAC和PHY的功能。-Based on the UDP FPGA network image transmission experiment, FPGA completed the RAW MT9V034 image acquisition cache, NIOS completed the image of the UDP packets, DM900
PS2shubiao
- 基于FPGA的PS2鼠标项目 EP4CE系列-PS2 mouse project based on FPGA
Stopwatch
- 在quatus平台，verilog语言编写的秒表代码。实现功能开始，暂停，复位，显示暂停。在Cyclone2上运行通过。-In quatus platform, verilog language stopwatch code. Achieve functional start, pause, reset, pause the display. On Cyclone2 run through.