资源列表
converter
- 多位2-10进制转换与10-2进制转换，用十进制加法器实现-2-10 and 10-2 convert binary number base conversion, decimal adder realization
multier
- 流水线高速并行乘法器，流水线设计，并行加法计算-High-speed parallel pipelined multiplier
SP605_V4_beifen_V2_success
- 基于FPGA内核microblaze的开发，使用的开发板是SP605，采用双备份冗余设计，实现了开发板上灯的控制。-Based on FPGA kernel MicroBlaze development, using the development board is SP605, the use of dual redundancy design, to achieve the development of the board on the light control.
USB Interface IP Core
- This module implements data receiving and transfering with cooperation of PIDUSBD12
adaptivefi-filter
- this code consists of adaptive fir filter algorithm using LMS based approach.
rc4
- RC4 is the most popular stream cipher in the domain of cryptology. RC4 consist of two algorithms Key Scheduling Algorithm (KSA) and Pseudo-random generation algorithm (PRGA).
Psoc-Design
- programmable silicon on chip documents
plj
- 频率计源代码，测量范围1hz-100Mhz，七位显示，三种量程，精度比较高-Frequency meter source code, measuring range 1hz-100Mhz, seven displays three range, high precision
adc0809_state
- 利用FPGA驱动DAC0832进行数据采样-Use FPGA drives DAC0832 sampling data
clk_even
- 利用FPGA编写的通用的偶分频，适合初学者使用-Even general division
yima
- 利用VHDL语言编写的译码程序，使用一位数码管进行显示-Using VHDL language decoding program that uses a digital display using VHDL language decoding program that uses a digital tube display
quanjia
- 通过VHDL语言编写的一位全加器程序，该程序是经过元件例化的方式实现-VHDL language through a full adder program, which is the result of component instantiation way to achieve