资源列表
clock_monitor
- 时钟监测模块，在系统运行过程中，时刻保持对时钟频率的检测-Clock detection module, the system is running, keep the clock frequency detection
inout
- 用于RAM的测试文件，以及testbench-some RAM testingfiles，and its testbench
FPGA_PWM
- 该代码的功能是在FPGA上实现PWM的功能，可以实现矩形波的占空比与频率可调。-The code function is to achieve PWM functions on FPGA, the duty cycle can be achieved with the adjustable frequency rectangular wave.
SOS
- 使用matlab生成SOS滤波器，应用于FPGA的一个小型系统，有一定的参考价值-Using MATLAB to generate SOS filter, applied to a small system of FPGA, there is a certain reference value
ahb_verilog_design
- 代码为ahb interface ，用verilog编写的,包括仿真和综合。-Code for the interface AHB, written in Verilog, including simulation and synthesis.
caacc
- cavcl entorpy coding
Soc_Audio_v5
- DE1 audio soc,xue xi audio process by Altera soc FPGA-DE1 audio soc
code
- 基本元器件代码包括iv nd2 alu acc fa lfsr mux21 等-The basic components of the code include iv nd2 alu acc fa lfsr mux21 etc.
pwm
- 通过该IP核输出三路pwm波，可用来控制一个舵机和两块L298N驱动板，从而控制电机。-IP core output by the three-way pwm wave can be used to control a servo drive plate and two L298N to control the motor.
Edge_Detection
- 信号的边缘检测，把一个频率较低的信号转为索需要的时钟频率的信号-Edge detection signal, the low-frequency signal into a signal cable required clock frequency
d_latch
- d latch digital circuits vhdl
four_bit_adder
- four bit adder digital circuits vhdl