资源列表
ioport
- FPGA开发所遇到的输入输出控制端口的VHDL代码,供大家学习借鉴!
combine_module
- 本代码根据包头、包尾指示，将两路数据合路调度成一路输出
Multiplexre_Examples
- vhdl codes for representing multiplexer using diffrent methods
filter
- 关于滤波器的verilog编程，对初学者很有用哦，从理论到实践的一次过度-Verilog programming on the filter, useful for beginners Oh, from theory to practice once over ...
FFT
- 使用Verilog硬件描述语言实现信号处理中的FFT信号的变换-Using Verilog hardware descr iption language conversion signal processing FFT signal
FFT2
- 适用于NIOS II的1024点FFT C算法- 1024-point FFT C algorithm for NIOS II
verilog_divdier
- veilog中的常用分频器，包括2分频 4分频 8分频等 开发环境为ise8.2-veilog commonly used in the dividers, including the 2 frequency divided by 4 divided by 8, such as development environment for ise8.2
lm75
- 基于FPGA的LM75温度检测程序，测试通过了，可用-FPGA-based LM75 temperature testing procedures, test passed, the available
seller2
- 程序实现自动售货机的核心功能，设有3种价格的商品，可选择数量，有找钱功能。-program vending machine at the core function, with three kinds of commodity prices, the number of choice, having to function.
iis_audio
- 24位立体声AD，IIS从模式数字音频数据接收。-24-bit stereo AD, IIS receives digital audio data from the model.
binary
- this is for low power dsp for wireless nodes (binary tree computation)
booth_mux4
- 基于verilog的4位booth算法编写-Written on verilog of 4 booth algorithm