资源列表
VerilogLabSource
- Verilog Lab Source Codes
final
- verilog code for finalisation
mux16
- 利用FPGA时序逻辑设计16位乘法器。利用时序逻辑设计可以使整体设计具备流水线结构-Sequential logic design using FPGA multiplier 16. Sequential logic design allows the use of the overall design with pipeline structure
ds18b20
- 完成DS18B20单总线温度传感芯片的控制和读取，将数据16位并行传出-Complete chip DS18B20 single bus temperature sensor control and read, 16 bit parallel data coming
moore_state_machine_v
- moor状态机的示例代码，再次基础上可以学习标准的状态机写法-moor state machine sample code, we can once again learning standards based on the wording of the state machine
tst_ds1621
- -- State machine for reading data from Dallas 1621 -- -- Testsystem for i2c controller--- State machine for reading data from Dall as 1621 -- -- Testsystem for i2c controller
3_Freq
- 3倍频实用稳定算法的VHDL实现（XILINX CPLD）
PCIInterface
- it is a vhdl code for interfacing plx chip with fpga
UDP_Core
- 本人用verilog编写的UDP协议，经测试可用。-I am prepared to use verilog UDP protocol, the test is available.
18B20PLCD
- 温度液晶显示演示程序 LCD数据线：P0口 LCD控制线：RS P20 RW P21 E P22 BUSY P07 18B20端口DQ ：P27 -Temperature of liquid crystal display demo Data line: P0 LCD LCD RS P20 RW P21 control line: E P22 BUSY P07 18B20 DQ : P27 port
SRC
- 流水线cpu 顶层模块verilog源代码，和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
WM8731 initialization file
- I2C initial WM8731 codec