资源列表
fadd
- 6级流水，verilog实现浮点数的加法，其中浮点数格式符合IEEE754标准
Practica_3
- SP converter in vhdl and counter and buffer
16DIANTIKONGZHI
- 16层电梯控制VHDL程序 内含各个模块的程序-16 floors of elevator control program includes modules in VHDL program
LPC_Host
- LPC总线，主机模块代码，VHDL语言描述-LPC bus, the host code, VHDL language descr iption
adder
- cpld/fpga常用加法器设计的verilog程序-cpld/fpga common adder Verilog design procedures
divide
- Verilog hdl语言的常用除法器设计，可使用modelsim进行仿真-Commonly used languages Verilog hdl divider design, can use the ModelSim simulation
clock
- vhdl做的简单的时钟，显示时分秒，可调时分，亮度。eda课程设计时所作。-vhdl do a simple clock display minutes and seconds, adjustable hours, brightness. eda made in curriculum design.
filter_stage1
- 虑波器，可综合代码风格，易懂，好理解。十六位的-Recorder, which can be integrated code style, easy to understand, easy to understand
xilinx_pci_exp_downstream_port
- //-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved. //-- This text contains proprietary, confidential //-- information of Xilinx, Inc., is distributed //-- under license from Xilinx, Inc., and may be used, //-- copied and/or disclosed
hamming_decoderhamming_encoder
- hamming_decoder hamming_encoder.rar 希望对大家有帮助-hamming_decoder hamming_encoder.rar hope to be helpful
state
- 这是SDRAM控制器的主状态机，里面包括了SDRAM的初始化程序以及最主要的状态机。-failed to translate
SVV_INFO
- System verilog questions