资源列表
Intro-VHDL-1
- Intro vhdl 1, electronic enginering
Intro-VHDL-2
- intro VHDL 2 , electronic enginering
Intro-VHDL-3-part1
- intro VHDL part 3 section 1, electronic enginering
Intro-VHDL-3-part2
- intro VHDL part 3 section 1, electronic enginering
Manual-VHDL
- Manuel VHDL, electronic enginering
counter8
- 使用vhdl语言和quartus平台建立的8位计数器的简单仿真-Using vhdl language and platform quartus established 8-bit counter simple simulation
fdivision
- 在quartus平台下，并使用verillog hdl编写的时钟分频仿真-In quartus platform and use verillog hdl write clock divider simulation
lcd-1602
- 关于用4端口对lcd1602显示，一般都是通过8端口显示的，上传的这个是ise里所建立的工程-On the use of the 4-port lcd1602 display, usually by 8-port display the uploaded this is ise in the established engineering
N-jifenpin
- 用verilog编写的N倍奇分频源码，大家可以参考一下哈哈哈。希望大神指正-With verilog written N times odd divider source code, you can refer to Ha ha ha. Great God hope corrected
RS232
- 用verilog编写的RS232串口通信源码，大家可以参考一下哈哈哈。希望大神指正-Verilog prepared using RS232 serial communication source code, we can refer to Ha ha ha. Great God hope corrected
mig_7series_v1_9
- DDR3控制器源码，针对XilinxFPGA的DDR3控制器的源码，已经验证通过。-DDR3 Controller，complete DDR3 controll，have pass verificaion.
uart_rx
- UART 接收模块，UART底层模块，实现各种波特率的uart接收-UART receive module，complete all Baud rate transfer receive。