资源列表
Vhdl_testbench
- vhdl 的testbench编写教程，英文ppt以及源码工程-Write tutorials, as well as English ppt Source of engineering vhdl testbench
GHDL
- quartus等文件业余爱好者测试仿真工具教程GHDL英文网站-quartus other documents amateur test simulation tools tutorial GHDL English website
uart
- 一种串行uart接口的实现，可支持对种通信速率，modlesim仿真-Realizing serial uart interface, which can support a variety of communication speed, modlesim simulation
7-BCD
- 7段数码管控制接口程序和对初始频率为50MHZ的时钟的分频程序-7-segment control interface program and the initial frequency of 50MHZ clock divider program
h_adder
- 基于两个半加器和一个异或门组成的全加器（资料中波形图为半加器的时序仿真图）-Based on two half-adder and an exclusive-or gate full adder (profile picture shows a half adder waveform timing simulation diagram)
IIR
- 基于nios ii嵌入式系统的IIR滤波器实现，自带ADC,DAC驱动代码-according nios ii
SATA_IP_FPGA
- SATA协议简要分析及其FPGA实现说明- SATA1.0 IP based on Fpga
SATA_Procotol_Summary
- SATA存储技术介绍文档，含协议及应用说明-SATA Technology
SATA3.0
- SATA3.0协议详细说明，PS：全英文介绍！-SATA3.0 Procotol
svpwm
- 永磁同步电机的SVPWM，电机的PWM波的产生程序，-Permanent magnet synchronous motor SVPWM, motor PWM wave generation program,
mux16
- 该程序中中就是要利用时序逻辑设计方法来设计一个 16 位乘法器-The program is to take advantage of the sequential logic design method to design a 16-bit multiplier
keyscanverilog
- verilog语言，在按键按下或者是释放的 时候都会出现一个不稳定的抖动时间，如果不处理好这个抖动时间，我们就无法处理好按键 编码，所以我们的设计中必须有效消除按键抖动。 -In the button is pressed or released When there will be an unstable time jitter, jitter if you do not handle this time, we can not deal with the key Codi