资源列表
06_pll_test
- PLL实现，在xilinx spartan 6的参考时钟50MHz上实现不同频率的锁相环程序-PLL implementation, in the Spartan Xilinx 6 reference clock 50MHz on the realization of different frequencies of the phase-locked loop program
FPGA-KZCJ
- NIOS2 FPGA控制TLC5540进行数据采集-FPGA TLC5540 control NIOS2 for data collection
FIFO-DOCUMENATATION
- DOCUMENTATION OF FIFO
MAC-DATA
- MAC UNIT DOCUMENTATION
bcd-doc
- BINARY TO BCD DOCUMENT
cbl-documentation
- COMMON BOOLEAN LOGIC DOCUMENTATION
binary-squarer
- BINARARY SQURING CIRCUIT DOCUMENTATION
CRC-DOCUMENTATION
- CYCLIC REDUNDACY CHECK DOCUMENTATION
brent_kung_add
- BRENT KUNG ADDER CODE
Adder-Designs-using-Reversible-Logic-Gates
- REVERSIBLE LOGIC BASED ADDERS DOCUMENTATION
FPGA_phase-shift
- 本文介绍基于FPGA和DDFS技术，应用Altera公司的FPGA开发工具DSP Builder设计数字移相信号发生器，该数字移相信号发生器的频率、相位、幅度均可预置，分辨率高，精确可调。-This paper introduces FPGA and DDFS technology based on FPGA development tools DSP Builder design of digital phase shift signal generator using Altera, fre
cpld
- 使用cpld完成多个串口切换通信，能够完成快速通信，已经完成验证-Using CPLD to complete multiple serial communication