资源列表
verilogfenpinqi
- verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation
digital_clock
- 本程序用VHDL语言实现数字时钟的功能，适用于ISE软件-This VHDL program has the function of digital clock and is suited for ISE software
jtag-Verilog
- JTAG verilog code for xilinx fpga
shouhuoji.vhd
- 自动售货机程序
addsub_28
- 一种用VHDL语言描述的加减算法的源代码编程-A VHDL language to describe the addition and subtraction algorithm source code programming
add
- Verilog hdl语言 常用加法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used adder design, can use the ModelSim simulation
data_swith
- verilog 代码实现串并转换，有延迟-Verilog code and string conversion, delay
create_200m
- 本代码用于产生FPGA内部的一个200Mhz的时钟，使得内部信号在此时钟下同步工作
GPIOROM
- verilog gpio source code verilog
BT656PcolorBarPFPGA
- Altera的EP2C5Q208C8芯片上跑通，后端接tw2880芯片输出上TV，进行验证无误。 i_pclk是27Mhz输入时钟，o_pclk是27Mhz输出时钟；i_clkin是笔者用的开发板50Mhz时钟，只用于生成稳定的复位信号。-Ran on Altera' s EP2C5Q208C8 chip pass, after termination tw2880 chip output on the TV, to verify correct. i_pclk 27Mhz in
RT-ADDRESS
- 芯片驱动控制程序 61580 1553b rt-61580 1553b rt
elevator
- 本人编写的verilog电梯程序，已仿真通过，欢迎大家下载学习，批评指正。-I write verilog lift procedures have been through simulation, welcome to download the study, criticism.