资源列表
Router
- 5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encoder-5 Pin Router with Virtual Output Queues 32 bit arbiter optional encoder and decoder also included along with priority encode
lfsrset
- Linear Feedback Shift Register
baugh_wool
- Baugh Wooley Multiplier
bfm
- Bus Functional Model Design
bzfad
- BZFAD Code in Verilog Possible Bugs
bzfadmultiplier
- BZFAD MUltiplier Code In Verilog Possible Bugs
Preemptive_answer
- 代码是多路抢答器,抢答精度极高，程序简单-primitive_answer
Viterbi_Decoder
- viterbi decoder for convolution encoder
AD_sampling
- 基于Verilog的AD采样FPGA程序,如果使用的话，FPGA接口重新设置即可-AD Sampling verilog program that is based on FPGA，if used，the IO Pins of FPGA should be redifined
bishe3
- 以复杂可编程逻辑器件(CPLD)为核心的新型通用数字触发器-Based on complex programmable logic device (CPLD) as the core of the new universal digital trigger
verilog-led
- 此程序是Verilog语言编写的一个流水灯程序，简单易行-This program is written in Verilog language a light water program, simple and feasible
PIPELINE
- （包含详细说明文档和简单汇编转机器码翻译器）五级流水线实现MIPS指令集（30条）含异常处理。结构采用多分支预测结构（基于历史的动态分支预测）-(Contains detailed documentation and compilation turn simple machine code translator) five pipelined MIPS instruction set (30) with exception handling. Structure using multi-bran