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  1. ieep1.3

    0下载:
  2. 10-b 50-MHz digital-to-analog (D/A) converter is presented which is based on a dual-ladder resistor string. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces th
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:494.6kb
    • 提供者:john
  1. ieep1.4

    0下载:
  2. 10-b binary-weighted D/A converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8-pm double-metal CMOS technology and the chip are
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:488.17kb
    • 提供者:john
  1. ieep1.5

    0下载:
  2. This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-pm double-poly double-metal CMOS technology. In the DAC, a new current source called the thresholdvoltage compensated current source is used in the two-stage current array to r
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:578.25kb
    • 提供者:john
  1. ieep1.6

    0下载:
  2. low-power 16-bit CMOS D/A converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric avera
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-03
    • 文件大小:623.63kb
    • 提供者:john
  1. morsecode

    0下载:
  2. 用DE2板,用SW0 到1表示想要的字母,KEY1运行,红灯显示对应的摩斯码,KEY0重置-With DE2 board with SW0 to 1 indicates the desired letter, KEY1 running red lights display the corresponding Morse code, KEY0 reset
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:1.25kb
    • 提供者:何亦嘉
  1. vga_adapter

    0下载:
  2. 可以用这个来把想要显示的图像显示在显示屏上。也可以用来做动画(画一帧擦一帧再移动再画)-You can use this to display the image you want to display on the screen. Can also be used to make the animation (painting a rub a painting and then move again)
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-26
    • 文件大小:11.86kb
    • 提供者:何亦嘉
  1. MMUMPU

    0下载:
  2. qsys with mmu mpu. Design in SOPC quartus 9.0
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-02
    • 文件大小:13.92mb
    • 提供者:jcc18
  1. wave_gen_vhd_s6

    0下载:
  2. 波形发生器,可以产生需要的波形,根据你的需要改变波的频率或者其他参数-as the same as its name
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:1.83mb
    • 提供者:郑岩
  1. clock

    0下载:
  2. 采用可综合的Verilog代码编写一个带闹钟功能的数字钟。使其具有以下功能: 1)计时功能:包括小时、分钟、秒钟。 2)校时功能:对小时、分钟和秒钟进行手动校时。 3)定时和闹钟功能:能在手工设定的时间产生闹铃音。 -Using synthesizable Verilog coding a digital clock with alarm. It has the following features: 1) timing functions include: hours, m
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.81kb
    • 提供者:shikai
  1. fu_dian_chu_fa

    0下载:
  2. VHDL浮点除法运算,VHDL浮点数除法,源码,含仿真图 -VHDL floating point division, source code, including simulation mapVHDL floating point division, source code, including simulation map
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-26
    • 文件大小:120.92kb
    • 提供者:钓江雪
  1. uart

    0下载:
  2. These codes are uart code written by verilog
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-14
    • 文件大小:3.22mb
    • 提供者:bdse98
  1. Microblaze

    0下载:
  2. FPGA Microblaze 硬件平台-Microblaze hardware
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-11
    • 文件大小:18.05mb
    • 提供者:fzm
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