资源列表
minimips_latest.tar
- minimalistic mips core. you can load it to any fpga.
vga-ok
- 详细介绍用FPGA实现VGA接口并显示图片-FPGA implementation details with VGA interface and display pictures
FPGA-FFT
- FFT算法详细介绍并用FPGA实现，包括FFT算法介绍-FFT algorithm is described in detail and with FPGA implementations, including FFT algorithm introduced
UART
- 用VHDL书写串口通信源码，在fpga上验证过-Serial communication with VHDL source code written in the fpga verified
jiaotongdeng
- VHDL书写的交通灯设计，适合初学者参考-Writing VHDL design of traffic lights, suitable for beginners reference
hanzi
- 使用VHDL书写的汉字滚动显示源程序，可以作为初学者参考-Using VHDL source code written in Chinese characters scrolling display can be used as reference for beginners
comparator
- FPGA比较器源码编写，适合初学者参考用,用ALTERA的QUARTUS 11.0编译-Compare FPGA source code written for beginners reference, compiled by ALTERA s QUARTUS 11.0
VHDL 1602
- VHDL的1602代码，基于FPGA的1602液晶代码
plj
- 时钟分频器原理与实现，计数跳变的频率和加减模式可实时变化，通过Nano实验板上的LCD显示器显示。计数频率、加减选择和初始化操作通过板上的拨动开关和Reset按钮实现。-Principle and Implementation clock divider, counting and addition and subtraction frequency hopping mode changes in real time, through the LCD display panel show Nan
qiangdaqi
- 基本功能： 1. 八路抢答器，同时供8个选手参赛，编号分别为1到8。每位选手用一个答题按钮和LED灯，选手按下时其灯亮。 2. 给主持人一个控制开关，实现系统的复位、抢答开始和分数清零。 3. 具有数据锁存和显示功能。抢答开始后，如果有选手按下了抢答按钮，其编号立即锁存并显示在LCD液晶显示屏上。此外，禁止其他选手再次抢答。选手的编号一直会保存，直到主持人清除。 -Basic features: 1. Eight Responder, while for eight contes
DE2_LED_sm
- 驱动DE2—70开发板上数码管，并设计了一个时钟计数器，时钟计数时，分，秒。-DE2 70 development board driver digital tube, and designed a clock counter, clock count, minutes, seconds.
CY7C68013andFPGAinterface
- CY7C68013与FPGA接口的Verilog HDL实现-Verilog HDL CY7C68013 and FPGA implementation of the interface