资源列表
DES-Verilog-master
- DES加密算法硬件verilog实现，包含testbench，加密主模块encrypt，明文变换模块LRToCiphertextConverter，NextRi模块等子模块。-DES encrypt verilog
lcd
- 采用Xilinx公司的Virtex-5芯片实现lcd程序-Using Xilinx' s Virtex-5 chip lcd procedure
UART-master
- UART通讯接口verilog代码实现，uart_tx子模块和uart_rx子模块，包含详细testbench-UART interface verilog code, uart_tx、uart_rx， testbench
gpio-master
- 基于WISHBONE总线接口的GPIO模块verilog代码实现，包含详细GPIO定义文档，testbench，RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
FSMpart2
- Verilog implementarion of FSM. Solution for altera s lab 7 part2.
part3FSM
- Verilog FSM implementation for altera s lab(part 3 of lab 7).
FSMpart4
- Verilog FSM implemetation for altera s lab 7(part IV) for de2115 fpga.
FSMpart5
- FSM Verilog implementation of the final part of lab 7 of altera s verilog tutorial for de2115 fpga.
sos_module
- 用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。-Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password,
TECOM
- fpga永磁同步电机转矩的控制算法，很实用-fpga pmsm te
7-segment-counter
- 7 segment counter in VHdl-7 segment counter in VHdl
crc16_d8
- 此代码采用Verilog语言实现8位CRC校验功能，采用CRC-ITU标准制定的CRC16校验-This code USES the Verilog language function of eight CRC check the CRC- ITU CRC16 calibration standards