资源列表
colorchecker
- coloecheck VGA格式标准色卡生成，可支持任意分辨率设置 verilog-colorchecker VGA format standard color card production, can support any resolution settings
gtx_drp
- 高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
pcie_ctrl_module
- pcie genx4 控制器模块 verilog，直接读取内存和写入内存-pcie gen4 controller module verilog, direct memory read and write memory
rs232-485-422
- 该文件含有串口收发编解码模块和自动识别波特率模块-This file contains the serial transceiver module and the codec module Automatic baud rate
Quartus_II_15.0_crack_Windows
- Quartus_II_15.0破解器_Windows版-Quartus II 15.0 crack for Windows
ZHWX
- DDS 产生正弦信号，OOK，AM三种波形。 使用xilinx FPGA VHDL-DDS. Resulting in sinusoidal signal, OOK, AM three waveforms. Using xilinx FPGA VHDL.
traffic
- 交通信号灯实验，南昌大学EDA课程，绝对有用-Experimental traffic lights, Nanchang University EDA course, absolutely useful
Tristate-buffers
- 本程序完成三态缓冲器的功能，采用硬件编程语言VHDL实现。-This procedure completion tristate buffers using hardware programming language VHDL implementation.
multichannel-selector
- 本程序实现了二选一多路选择器的硬件功能，采用VHDL语言编写而成。-This program implements a second election multiplexer hardware function, written in VHDL language.
Serial-borrow-eight-subtracte
- 本程序实现了串行借位的八位减法器，采用VHDL语言实现。-This program implements eight serial borrow subtractor, using VHDL language.
Digital-clock
- 利用Quartus编程软件及EDA实验板（芯片为EP1C6Q240C8）完成数字钟设计，该数字钟有显示时、分和秒的功能。-When the Quartus programming software and EDA experiment board (chip EP1C6Q240C8) complete digital clock, digital clock showing the hours, minutes and seconds functions.
My-And
- And port made with nand gates in Verilog