资源列表
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
traffic
- 模拟交通灯 verilog CPLD EPM1270 源代码-Simulation of traffic lights verilog CPLDEPM1270 source code
8ENCODE
- 8位优先编码器 verilog CPLD EPM1270 源代码-8-bit priority encoder verilog CPLDEPM1270 source code
chuankou
- 串口VHDL实现 -Serial Serial VHDL realization of VHDL
mux21a
- 二选一多路选择开关，实现对信号的采集，分类。-Second, the election more than one way selector switch, to achieve signal acquisition, classification.
VHDL
- 一个实现整数分频的VHDL代码，只要把n设置成你所需要的分频的数值就行-A realization of an integer divider of the VHDL code, as long as the n set you need the sub-frequency values on the line
FPGA
- fpga 设计经典指导原则，非常经典，对于深入理解FPGA设计方法有很好的帮助-FPGA design of the guiding principles of the classic, very classic, for better understanding of FPGA design methods have a very good help
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
fifo
- 此程序为存储器常用的FIFO（先入先出），程序中没有指明位宽，这样更适合于初学者进行套用-This process commonly used for the memory FIFO (FIFO), the procedure is not specified bit, so more suitable for beginners to apply
moore_in_and_mealy_out_state_machine
- 此程序为带摩尔输入、米勒输出状态的状态机控制部分-This procedure with Moore for input, Miller output state control of some of the state machine
mealy_state_machine
- 本程序为米勒状态机经典设计模块，对用状态机设计程序控制部分具有指导意义-This procedure for Miller classic state machine design modules, using state machine control part of the design of guiding significance for
OPERATION_UNIT
- 本程序为加密芯片内部加密运算单元部分，包括32位减法器、移位寄存器、加/减法器、寄存器等，对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and so on password-chip design has