资源列表
KEYBOARD
- 键盘扫描程序，该程序可以对4*4的键盘进行扫描-Keyboard scanning process, which can be 4* 4 keyboard scan
source
- verilog HDL example .many module .
20081023154349131
- EDA中的45 s定时单元的VHDL源程序-EDA in the 45 s timer unit VHDL source code
cpuyuanma2
- 这是接上面程序，是微程序控制器源代码，调试已经通过。-This is then the above procedures, micro-program controller source code, debugging has been adopted.
PCR
- 本程序是在传输流传输过程中对节目时钟字段进行检测与修改,采用Verilog HDL 语言进行编程。-This procedure is in the transport stream during transmission of program the clock to carry out field testing and modification, using Verilog HDL language programming.
div_clk
- 主时钟为15.36MHz的带选通的8位输出分频器，可得到100Hz,120Hz,1kHz,10kHz的频率-Master clock for the 15.36MHz band strobe output 8-bit prescaler, can be 100Hz, 120Hz, 1kHz, 10kHz frequency
count_binary_0
- 二进制计数器的硬件代码，可在ISE或quartus下完成调试-Binary counter hardware code, available at ISE or Quartus to complete debugging
niosII_system_cpu
- cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
cpu_0
- cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
jtag_uart_0
- jatag在nios环境下的接口代码，可在ISE或quartus下完成调试-Nios jatag environment in the interface code, can be accomplished under the ISE or Quartus debugging
onchip_memory_0
- 在线仿真调试的存储器代码，可在ISE或quartus下完成调试-Online simulation of the memory debugging code can be accomplished under the ISE or Quartus debugging