资源列表
adder1
- 一个全加器的VHDL程序,经过编译和仿真.-A full adder of the VHDL program, after compiling and simulation.
clk_8
- 一个八分频的VHDL程序,经过编译和仿真.-An octant of the VHDL-frequency procedures, after the compiler and simulation.
zhiliu_dianji
- 直流电机的VHDL源程序,经过编译和仿真.-DC motor VHDL source code, after compilation and simulation.
RAM
- 双口RAM与PXI总线接口设计，包括接口控制。-Dual-port RAM with PXI bus interface design, including interface control.
vhdl
- 学习vhdl硬件描述语言的一些例子的原代码-VHDL hardware descr iption language to learn some examples of the original code
clock
- XLINX做的数字钟，可以准确计时的。 用计数器和触发器实现。-XLINX do digital clock can be accurately timed. With counters and flip-flops to achieve.
digitalclock.vhd
- 实现电子钟的功能，使用VHDL编程语言，调试已经通过-Electronic clock function, the use of VHDL programming language, debugging has been passed
EBCode21
- 功能很强大！！！希望大叫多多指教，共同进步，一块发展-Function is very powerful! ! ! Hope that the exhibitions shouting and common progress, a development
Digital_signal_processing_with_FPGA
- 个人觉得对C的学习者有很大的帮助，是我收藏的经典之作，希望对大家有所帮助-Personally feel that for C learners be very helpful to my collection of classic, I hope all of you to help
veriloghdl
- 关于vhdl很好的一个课件，希望对大家有用-On a VHDL good courseware, in the hope that useful
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
EP3C25
- Cyclone® III EP3C25的资料-Cyclone 庐 III EP3C25 information