资源列表
pll
- 收集的数字锁相环设计相关文章多篇.主要采用VHDL语言进行设计.-Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
111
- 51单片机设计的电子密码锁 -51 Single-chip design of the electronic code lock
rs232_rec5
- VHDL语言实现的穿行通讯，可实现闭环操作，通讯过程中每个bit位采样3次，保证数据准确。-VHDL language achieved through communication, can realize the closed-loop operation, communication process each bit digital sampling 3 times to ensure accurate data.
a
- ADPLL of high level phase locked loop
alu
- 用VHDL实现8种运算的ALU，带鱼不带符号的加减乘除，与或异或和求反-Use VHDL to achieve the eight kinds of computing ALU, hairtail unsigned addition and subtraction, multiplication and division, with or XOR and seek anti-
fpga-plus
- 讲述fpga的幻灯片，很有用的讲解。主要涉及到fpga-plus方面的知识。-FPGA on the slide, very useful to explain. Mainly related to fpga-plus kinds of knowledge.
paobiao
- 给出了数字跑表的源代码，设计了分频模块，实现了真实的时间计数，通过这个工程的训练，能更好的了解Quartus II数字电路开发的过程。-Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quart
mux
- 多路选择器是一个多输入，单输出的组合逻辑电路，在算法电路的实现中常用来根据地址码来调度数据。-MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
fcsr
- 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
53lift
- 几篇关于5，3小波FPGA硬件实现的文章，很有帮助-5,3 wavelet few on FPGA hardware implementation of the articles, very helpful
FFT_VHDL
- fft是基本的信号处理算法，本程序为fft算法的VHDL语言-fft is a fundamental signal processing algorithms, the procedures for the fft algorithm VHDL language