资源列表
timer_0
- 计数器的FPGA控制程序，开发平台为ISE或者quartus-FPGA counter control procedures, development platform for the ISE or Quartus
CPLDVHDLCODE
- CPLD VHDL CODE非常好的参考资料-CPLD VHDL CODE a very good reference
Triangle_Wave_generater
- 采用vhdl语言编程，基于quartus平台的三角波仿真。-Using VHDL language programming, based on the Quartus triangular wave simulation platform.
Synplify
- 华为synplify入门教程：Synplify快速入门-Huawei Synplify Tutorial: Synplify Quick Start
hdb3_1.1
- verilog 语言hdb 3 编 码 经过测试，但冗余问题未解决-Verilog language coding hdb 3 tested, but unresolved questions redundancy
clock
- 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
miniUART
- 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
VHDL
- 适合VHDL开发的中级教程,是比较经典的书籍-Intermediate VHDL for the development of curriculum, which is a more classic books
MAXPLUS
- MAX+PLUSⅡ的学习应用教程,适用于基本的VHDL开发-MAX+ PLUS Ⅱ Application Tutorial learning for the development of the basic VHDL
Dualpriorityencoder
- 用VHDL编译的源代码，两位优先级编码器，输入一个十进制数，直接显示头两个‘1’所在的位，解压后直接用Quartus打开project即可-Compiled with VHDL source code, the two priority encoder, enter a decimal number, direct show
fourbitincrement
- 用VHDL编译的源代码，4bit加一器，输入一个4位二进制数自动加一，解压后直接用Quartus打开project即可-Compiled with VHDL source code, 4bit-plus-one, and enter a 4-bit binary number plus one automatically, after extracting the direct use of Quartus can open the project
heartbeat
- 用VHDL编译的源代码，模拟心脏跳动，解压后直接用Quartus打开project即可，不好意思刚才第一个那个模拟心脏跳动（heartbeat）的源程序发错了，请删除，-Compiled with VHDL source code to simulate the beating heart, after extracting the direct use of Quartus can open the project, I am sorry but the first one that simu