资源列表
RESPONGDER_ZJDD(6.28)
- 实现思路多功能抢答器，基于FPGA开发板上的VHDL语言设计，主要功能有在抢答和回答倒计时内四个选手按键进行抢答，由主持人按键进行抢答开始和结束；附加有回答问题，在LCD12864上显示问题答案及各组分数等。-Realization of ideas multifunction Responder, FPGA-based development board of the VHDL language design, the main features are the answer and the
SMART_L1B_SL_0002
- coware 处理器模型库, 为处理器开发提供支持-coware processor model libraries, support for the processor development
multiplier
- Booth乘法器是属于位操作乘法器，采用流水线结构实现(The Booth multiplier is a bit-operated multiplier that is implemented in a pipeline structure.)
TCAM
- 基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示-TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions
ExtremeEDA100-SystemC_UT_Intro
- ExtremeEDA的系统建模与systemC语言教程讲义，内容包括系统建模概念，systemC语法以及应用实例-System modeling and systemC ExtremeEDA language tutorial handouts, including system modeling concept, systemC syntax and examples
ADCnCLK
- ADC 采样，48M时钟提供, 采用 差分信号传输-ADC sample , for 48 M clock
DE2_115_Audio
- FPGA开发板所带的示例程序，实现音频信号的采集，处理和输出，用verilog语言编写，可直接编译下载，非常有学习和参考价值-FPGA board comes with sample programs, audio signal acquisition, processing, and output, using Verilog language can be compiled directly download very learning and reference value! ! !
ChuZuCheJiFeiQi
- VHDL描述出租车计费器，12864显示-VHDL descr iption of a taxi meter, 12864
SEG7
- 基于xilinx的开发板，利用verilog语言实现扫描数码管，小键盘和计数的功能-Xilinx development board based on the use of digital scanning verilog language, keypad and counting functions
tPad_Picture_Viewer
- tPad DE2-115/70可用的图片浏览设计程序，原装程序，可下载到带触摸板的DE2开发板上调试，代码可修改-tPad DE2-115/70 picture browsing design program available, the original program, with a touch pad can be downloaded to the DE2 board debugging, code can be modified
uart
- FPGA基于串口指令的多电机闭环调速系统-FPGA based multi-port instruction Motor Closed Loop System
shuzizhong
- 实现数字钟设置与查看 秒表 以及闹钟设置与查看-Digital clock stopwatch and alarm clock