资源列表
Zybo_Pmod_CAM_0.3M_QVGA
- zybo开发板，采用ov7725低照度摄像头，搭建图像采集和显示系统-zybo development board, using ov7725 camera illumination, image acquisition and display system built
code
- 多波形信号发生器，通过FPGA实验箱来开发，可以实现按键控制波形的输出-Multi-waveform signal generator, through the FPGA to develop experimental box, you can achieve an output waveform control buttons
cpuTerminate
- 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
223
- 正交频分复用的硬件描述语言实现(Altera环境)-Orthogonal frequency division multiplexing hardware descr iption language (Altera Environment)
32_bit_mpu
- I got my semester project on IMPLEMENTATION OF 32 BIT MIPS processor and implementation on XILINX spartan 3e.i made thys code on verilog and includes LCD interfacing with the kit
CPLD_example
- CPLD源代码，内有转换开关、LED、计数器、蜂鸣器、数码管动态显示、音乐、LCD等代码-CPLD source code, the changeover switch, LEDs, counters, buzzers, digital tube dynamic display, music, LCD and other code
fftprocessor_latest.tar
- fast fourier transform
SONGER
- 利用ABEL语言设计一个多模计数器，对实验台上的100KHz进行分频，产生8种希望的频率。将8种频率的信号输入喇叭，产生8种不同声音，驱动喇叭的方波占空比应是50％，以增大音量。频率调制成功后，将8种音调按一定的优先级输出。-ABEL language use to design a multi-mode counter, the experimental stage 100KHz dividing to produce eight kinds of the desired frequency.
lab7_files
- 关于Digilent Atlys Spartan-6 FPGA development board audio ac97的讲解及具体应用的源码-Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code
143637___fpgas_and_cplds
- vhdl couter 3 bit and make by vhdl and vhdl
DE2_NIOS_HOST_MOUSE_VGA
- 用Vrilog实现了在显示器上用鼠标画图，开发环境是DE2-70-DE2-70 development environment to achieve a draw with the mouse on the display with the Vrilog
SUS2
- IT VERY NICE FOR VHDL.