资源列表
New-WinRAR-ZIP-archive
- snake game with two backgrounds-snake game with two backgrounds
intro_to_quartus2_chinese
- ALTER公司的官方版Quartus® II 简介，包括基本的设计流程，布线等 -ALTER s official version of the Quartus® II profile, including the basic design process, wiring and so on
FPGA-UART
- 该资料是实现VHDL的串口通信(UART)，RS232接口协议，-VHDL implementation of serial communication
FPGUART
- verilog语言，FPGA，串口。 波特率9600，数据位8位，停止位1.-verilog language, FPGA, serial. 9600 baud, 8 data bits, 1 stop bit.
TUSB9260
- Ti的USB3.0解决方案，基于TUSB9260，包含参考电路设计与应用指南。-Ti, USB3.0 solutions, based on the TUSB9260, including reference circuit design and application guide.
mycfft
- LTE通信中的cfft算法的VERILOG实现，具有一定的参考意义。-LTE communication in the VERILOG algorithm CFFT implementation, with a certain reference value.
viterbi_soft
- (2,1,3)卷积码编码，软判决译码；matlab语言编码；verilog语言译码；-(2,1,3) convolutional code encoding, soft-decision decoding matlab coding verilog decoder
dds1
- SPARTAN-3E DDS matlab生成的coe文件-SPARTAN-3E DDS coe by matlab
8051_test2
- 基于FPGA模块实现仿真8051单片机的程序。-The FPGA module to realize the simulation of 8051 program based on single chip
DEADTIME510
- 产生全桥逆变电路的驱动脉冲信号，能够保证死区时间，且随输入信号频率的变化而变化。-Produces full-bridge inverter circuit driving pulse signal, to ensure that the dead time, and with the input signal frequency changes.
SOPC_LCD
- 基于SOPC构建的CPU，用DE2-70做的LCD显示，用c语言进行编写。-Based on SOPC built CPU, LCD display with DE2-70 do with the c language written.
newsdram
- 8读8写SDRAM verilog 程序