资源列表
XAPP211
- Xilinx APP Generators Using the SRL Macro
XAPP204
- Using Block RAM for High-Performance Read.Write Cams
XAPP217
- Gold Code Generators in Virtex Devices
XAPP220
- LFSRs as Functional Blocks in Wireless Applications
XAPP289
- Common Switch Interface CSIX-L1 Reference Design
planeAgc
- AGC的vhdl实现，给大家提供思路的,希望对大家有帮助-agc in vhdl.
fifo_Cprogram
- 应用于nios中的FIFO程序及连接图，开发环境为quartus-c program fifo in nios
XAPP146
- 8 Channel Digital Volt Meter
Fourinputandnongatecircuit
- VHDl编写的四输入与非门电路，其代码简洁，易学易懂-VHDL prepared four input and non-gate circuit, and its code is simple and easy to understand
SingleclocksynchronousdesignmetricCNTR
- 用VHDL 设计的单时钟同步十进制可逆计数器的设计-VHDL design using a single clock synchronization decimal CNTR Design
EP1C6_12_1_2_MOTO
- 基于ALTERA的cyclone 系列的控制电机的实验例程-ALTERA series based on the cyclone motor control routine of the experiment
Quartus_Clock
- 利用Quartus模块化层次化设计数字钟-Using Quartus hierarchical modular design digital clock