资源列表
xapp345_verilog
- Synthesizable Verilog UART source code.
xapp223
- UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buffer for Virtex, Virtex-E and Spartan-II FPGAs-UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buf
FIFO
- 用verilog语言编写的FIFO文件，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令，希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, h
FSM
- 用verilog语言编写的FSM文件，有限个状态及在这些状态之间的转移和动作等行为的数学模型，在计算机领域有着广泛的应用。-Mathematical model with verilog language FSM file transfer and finite number of states and actions between these states and other behavior in the computer industry has a wide range of appl
CLA_20
- 用verilog语言编写的CLA_20文件。CLA_20是20位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 20 files. CLA 20 is 20 lookahead adder source code after the code verification function correctly, readers can write their own testbench code fo
CLA_4
- 用verilog语言编写的CLA_4文件。CLA_4是4位超前进位加法器的源代码，该代码验证后功能正确，读者可以自行编写testbench代码进行验证。-With verilog language CLA 4 files. CLA 4 is a four-ahead adder source code after the code verification function correctly, readers can write their own testbench code for ver
temp
- temprature converter VHDL code
alu1
- VHDL Code for ALU -VHDL Code for ALU .......
digital-clock
- Digital clock vhdl code
traffic
- traffic vhdl code -traffic vhdl code ......
kb
- 基于niosII系统的PS2键盘测试程序，测试PS2键盘与niosII内核的通信是否成功。该程序在Quartus自带的eclipes下编译运行。-Based nios II system PS2 keyboard test procedures, test PS2 keyboard and niosII kernel communication is successful. Compile and run under Quartus comes eclipes.
12_24clock
- 基于FPGA的数字万年历设计。可显示年月日时分秒星期，可校时，可整点报时。-FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping.